The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the inventors hereof, to the extent the work is described in this background section, as well as aspects of the description that does not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted to be prior art against the present disclosure.
Frequency synthesis is widely used in computing devices, such as wireless communication devices, medical devices, and so on. For example, a computer central processing unit (CPU) can be configured to generate a 1 GHz clock from a 100 MHz reference clock via frequency synthesis. A phase-locked loop (PLL) is a common type of a frequency synthesizer. A PLL typically employs a negative feedback system that locks the phase and frequency of a first signal to a second signal. In a typical PLL, the frequency of a signal output from the PLL tracks the phase and frequency of a reference input clock signal that is input to the PLL such that the rising edges of the output signal, which is fed back to the PLL, are aligned to the rising edges of the reference input clock signal. Oscillators typically are used to generate the input clock signal, or the output clock signal. However, some oscillators, such as a voltage-controlled oscillator (VCO) employed to generate the output signal, are generally sensitive to various factors such as temperature, noise in power supplies, electro-magnetic interference, etc., and thus the output signal of the VCO can sometimes be unstable, whether because of such environmental factors or because of cross talk and/or interference as a result of interaction with signals generated by other oscillators on the same electronic device. For example, when environmental noise and/or other unwanted signals enter a VCO, a spurious aberration, e.g., a “spike,” can sometimes be observed in the signal power spectrum of the output clock signal from the VCO, which is referred to as “spurs” throughout this disclosure. The oscillator-induced spurs in the PLL negatively impact the performance and accuracy of the PLL.